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Time Protection
aka Timing Channel Prevention


Design, implementation, evaluation and verification of black-box OS abstractions and mechanisms for preventing timing channels.



A timing Channel based on cache contention

Micro-architectural timing channels result from competing access to shared, finite hardware resources. Sharing may be time-multiplexed (intra-core) or concurrent (inter-core).

Unauthorised information leakage is a violation of a system's security policy (see the background page for further explanation). Enforcing security is a primary responsibility of the operating system (OS); yet no contemporary, general-purpose OS has the means for preventing this violation. Our aim is to change this.

Our formally verified seL4 microkernel provably prevents other security violations, including through covert storage channels. This makes timing channels the last, fundamentally unsolved security problem in operating systems, and seL4 the ideal platform for solving it.

In particular, the OS must provide mandatory enforcement of timing-channel freedom, i.e. security enforcement must not depend on application cooperation. Mandatory enforcement is the only way to ensure that untrusted code operating on secret information does not leak it. Such code is commonplace: legacy software stacks running on untrustworthy mainstream OSes such as Linux, Macos or Windows, smartphone apps, browser plugins and server-provided Javascript routinely process confidential data. Furthermore, the use of gadgets in the Spectre attack has shown that even supposedly trustworthy code can be turned into a Trojan.

Hence we are looking for black-box OS-level mechanisms for providing temporary isolation. For spatial isolation such mechanisms are well-established, the core mechanism is memory protection. Here we are working on providing the corresponding temporal isolation, which we accordingly call time protection.


Our earlier investigations have shown that complete time protection is not possible on present hardware, hence solving this problem requires a hardware-software co-design approach. In other words: we need a new, security-oriented, hardware-software contract.

Consequently, we are pursuing a number of directions concurrently, with the ultimate aim of verified time protection.

Hardware-software contract

  • We have defined the high-level properties of the HW-SW contract that the OS needs to provide time protection.
  • We are working with the PULP team at the Integrated Systems Lab of ETH Zurich on a processor that provides sufficient mechanisms to allow the OS to provide full time protection. This will based on ETH's Ariane, a 64-bit RISC-V CPU.
  • We are active on the RISC-V Foundation's Security Standing Committee to ensure the architecture will provide the right mechanisms, and help make RISC-V the most secure processor architecture.

OS mechanisms

We have designed and implemented (in seL4) fundamental time-protection mechanisms. These consist of:

  • A new kernel clone mechanism that provides a policy-free way of setting up a system without any memory shared between security partitions (save a small number of kernel data structures that are accessed carefully to ensure deterministic execution). This eliminates any channels through a shared kernel image.

    Kernel cloning provides a way of identifying security-domain switches, thus informing the kernel at which context switches additional scrubbing operations are needed. This is a policy-free way of minimising isolation overheads.

  • Security-partition switches that Careful reset all shared micro-architectural state, while making switch times completely deterministic, and in particular, independent of previous execution history.

  • Mechanisms for partitioning lower-level caches, where flushing cost would be high and would not help if those caches are shared across cores. This employs page colouring, and extends to kernel code and data.

  • Partitioning of interrupt sources, so the system is able to use interrupt-driven I/O, unlike classical separation kernels, which disable all interrupts and rely on high-overhead polled I/O.

We have demonstrated that these mechanisms are effective, to the degree that the hardware provides the right mechanisms for scrubbing or partitioning state.

OS Abstractions

Having developed seL4 mechanisms able to provide time protection, we now are working on suitable abstractions that integrate with the existing seL4 model, in particular the new scheduling-context capabilities that provide a principled treatment of time as a resource, with the aim of supporting mixed-criticality real-time systems.

Our aim is a similarly principled model that combines both types of temporal isolation, temporal integrity for real time, and temporal confidentiality for security.

Verifying time protection

The ultimate aim is to be able to prove that our system provides complete time protection. This will require formally specifying the hardware-software contract (at as abstract a level as possible), including formally defining partitionable vs flushable hardware resources.

Specifically we are working on a operational specification of the required properties, so that time protection can be verified as a functional-correctness property without explicit reasoning about time. This approach will allow us to extend seL4's existing proofs of information flow security to also provide assurance about timing channels.

Preparatory work


When we started this line of work a few years ago, we provided a formal proof of the absence of side channels using a lattice scheduler. However, this work is based on idealised hardware.


We also empirically investigated a number of defence mechanisms suitable for black-box enforcement. The evaluations showed that these mechanisms are effective on some hardware, but fail to close channels completely on other.

Survey of attacks

In order to better understand the problem we conducted a comprehensive survey of micro-architectural timing channels.

Assessment of hardware mechanisms

Following the discovery that our defence mechanisms were not fully effective, we conducted a thorough analysis of microarchitectural timing channels of multiple generations of Intel and ARM processors. We examined the mechanisms provided by the hardware and measured their effectiveness. Our results show that all microarchitectural state we examined can be used for timing channels, including two channels (TLB and branch target buffer) that have not been demonstrated before.

More importantly, our investigation uncovered on each examined platform at least one channel that cannot be closed with any state-flushing operation provided by the hardware. This is summarised in an arXiv paper, and we provide the complete, updated results.


Abstract PDF Qian Ge, Yuval Yarom, Tom Chothia and Gernot Heiser
Time protection: The missing OS abstraction
arXiv preprint arXiv:1810.05345, October, 2018
PDF Qian Ge, Yuval Yarom and Gernot Heiser
No security without time protection: we need a new hardware-software contract
Asia-Pacific Workshop on Systems (APSys), Korea, August, 2018
Best Paper Award! Complete timing-channel data for evaluated x86 and Arm platforms.
Abstract PDF Qian Ge, Yuval Yarom, David Cock and Gernot Heiser
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware
Journal of Cryptographic Engineering, Volume 8, Issue 1, pp. 1-27, April, 2018
Abstract PDF Gernot Heiser
For safety's sake: we need a new hardware-software contract!
IEEE Design and Test, Volume 35, Issue 2, pp. 27-30, March, 2018


Abstract PDF Qian Ge, Yuval Yarom, Frank Li and Gernot Heiser
Your processor leaks information — and there's nothing you can do about it
arXiv preprint arXiv:1612.04474, 2017


Abstract PDF Fangfei Liu, Qian Ge, Yuval Yarom, Frank Mckeen, Carlos Rozas, Gernot Heiser and Ruby B Lee
CATalyst: defeating last-level cache side channel attacks in cloud computing
IEEE Symposium on High-Performance Computer Architecture, pp. 406–418, Barcelona, Spain, March, 2016


Abstract PDF Yuval Yarom, Qian Ge, Fangfei Liu, Ruby B. Lee and Gernot Heiser
Mapping the Intel last-level cache
The Cryptology ePrint Archive, September, 2015
Abstract PDF Fangfei Liu, Yuval Yarom, Qian Ge, Gernot Heiser and Ruby B Lee
Last-level cache side-channel attacks are practical
IEEE Symposium on Security and Privacy, pp. 605–622, San Jose, CA, US, May, 2015


Abstract PDF David Cock, Qian Ge, Toby Murray and Gernot Heiser
The last mile: An empirical study of some timing channels on seL4
ACM Conference on Computer and Communications Security, pp. 570–581, Scottsdale, AZ, USA, November, 2014
Abstract PDF David Cock
Leakage in trustworthy systems
PhD Thesis, UNSW, Sydney, Australia, August, 2014
Abstract PDF David Cock
From probabilistic operational semantics to information theory — side channels with pGCL in isabelle
Proceedings of the 5th International Conference on Interactive Theorem Proving, pp. 1–15, Vienna, Austria, July, 2014


Abstract PDF David Cock
Practical probability: Applying pGCL to lattice scheduling
Proceedings of the 4th International Conference on Interactive Theorem Proving, pp. 1–16, Rennes, France, July, 2013


Abstract PDF David Cock
Verifying probabilistic correctness in Isabelle with pGCL
Proceedings of the 7th Systems Software Verification, pp. 1–10, Sydney, Australia, November, 2012


Abstract PDF David Cock
Exploitation as an inference problem
4th Workshop on Artificial Intelligence and Security, pp. 105–106, Chicago, IL, USA, October, 2011
Served by Apache on Linux on seL4.